Xilinx FPGA XCVU19P PCIe Design
Xilinx Uleashes Worlds Largest FPGA:
The Virtex Ultrascale+ VU19P 8.938-Million Logic Gates/Cells
Xilinx FPGA XCVU19P PCIe Design the Virtex UltraScale+ VU19P FPGA provides the highest logic capacity, interconnect, and external memory bandwidth available in an FPGA—9M system logic cells, 2,072 I/Os, and 80 high-speed transceivers.
The Virtex UltraScale+ VU19P FPGA is built for the most bandwidth, logic, and interconnect intensive workloads.
While this FPGA is tuned for ASIC/SoC emulation and prototyping, test and measurement, it is also suited for applications such as compute, networking, and aerospace & defense.
This is Xilinx's 3rd generation of the highest capacity FPGA. Through a combination of third-generation stacked silicon interconnect (SSI) technology and co-optimized with the VIvado® Design Suite, Virtex UltraScale+ VU19P FPGA offers a mature, comprehensive solution to enable tomorrow's most complex ASIC and SoC technologies.
Xilinx introduces the Virtex® UltraScale+™ VU19P, the world’s largest FPGA, to enable prototyping and emulation of the most advanced ASIC and SoC technologies, as well as the development of complex algorithms.
The VU19P FPGA provides the highest logic density and I/O count on a single device ever built, addressing new classes of demands in the evolving technologies.
We do not often cover the FPGA market commerce, but here at CryptoUranus, in the past couple of years we have seen the array of features that FPGAs are implementing expand at an incredible rate.
The Chinese company Xilinx has been at some of the forefront of those innovations years ahead of the entire worldwide FPGA technology, with products such as Versal on 7nm and its Alveo family.
Xilinx’s business profile is emulation, simulation, and implementation directed at their advanced miltary applications and the less advanced technology grouped into civilian enterprise applications here XCVU19P FPGA chip.
This requires Xilinx to produce more advanced FPGAs to fit large designs onto - and the company recently lifted the lid on its latest creation, the Virtex Ultrascale+ VU19P.
This new FPGA, when it comes to market, will hold the title of the World’s Largest FPGA, and again pushing United States of America technology designs years behind Xilinx even further; shocking in the least.
Large FPGAs are Big Business
The FPGA defined is a "Field Programmable Gate Array", and this is a chip on a breadboard with other hardware that allows circuit designers to create more advanced forming hardware.An FPGA is the most programmable hardware on earth to date that a user can design any integrated circuit imaginable onto the FPGA board, debug it, tweeak out errata flaws before the design goes to market.
Chinese engineers can avoid design flaws and make technology that works with far less flaws.
The FPGA's avoids get rough estimates on performance and accuracy before assembly lines create products to avoid hardware recalls and-or money consuming redesigns and-or upgrades costing the entire industry over-spending.
One of the biggest FPGA today on Xilinx’s 22nm-based production line is the Virtex Ultrascale+ 440, an engineer can simulate over 10 concurrent Arm Cortex A9 cores within the FPGA for testing purposes as most FPGA are used for.
With this new advanced UltraScale+ VU19P, that same engineer can simulate over 16 of the same cores, due to the 1.6x increase in logic gates.
FPGAs act as a base for the latest designs and technologies to test and simulate before production, with specific IO logic that can be built into current and future communication technologies.
The design of an FPGA makes it more engineer friendly and configurable than a any CPU, GPU, and assorted other programmable IC chips.
Within this perspective the FPGA configuration can then be taken onto fabrication assembly and made into an optimized chip for better performance and density before ever solidified into an actual physical product.
Ultimately in order to design a CPU, you need an FPGA.
In this announcement, Xilinx has explained to a huge audience that a sizeable part of its business is catering to this simulation and emulation market.
This FPGA IC is used by chip vendors globally more the Intel designs do to U.S. wasteful inefficient industrial spending costs.
Xilinx, the venture creating larger chips gave them the engineering carnered market creating the VU19P placing them, again, ahead of all U.S. technology groups.
The VU19P is actually built as four segments then placed on a die, however the chip acts as one seemless large piece of silicon, totaling 35 billion transistors.
The Xilinx VU19P along with the 8.938m logic gates, there is also over 2000 IO segments for 4.5 Terabits of transceiver bandwidth (80 lanes of 28G) and 1.5 Terabits of DDR4 memory bandwidth leaving the United States in the dust again, sadly enough.
Xilinx company states that it will help its customers create designs featuring multiple VU19P chip sales into the global industry in one single system with all-to-all connectivity topology unlike no other company will on earth.
In PCIe card form the VU19P can be built as either a PCIe 3.0 x16 or PCIe 4.0 x8 device, and also as a separate chip it can be used in a 65x65 package with a BGA3825 connection with the potential for CCIX connectivity.
The CVU19P hardware features include 8.2m CLB Flip-Flops, 4.1m CLB LUTs, 90 Mb of high-speed UltraRAM, 40 Clock Management Tiles (CMTs), and 3840 DSP slices.
Some of those numbers are quite a bit smaller than the UltraScale+ VU13P, which has only 4m logic gates, but this is due to the balancing of resources which Xilinx states will favor the simulation and emulation market.
With the VU19P, the Xilinx company will also make enhancements to its Vivado Design Suite software to assist with co-optimization of the new chip design in their leading global place.
Xilinx is set to bring the VU19P to market in the fall of 2020 (~Q3), and will be ready to start sampling key partners in the first half of 2020.
I found a chip. It's @XilinxInc's new 'biggest FPGA ever', the Virtex Ultrascale+ VU19P with over 9 million logic cells, 35 billion transistors, and 80 x 28G IO.
Built on TSMC 16FF+, coming in Q3 2020.
